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MOSEL VITELIC
V53C16258L HIGH PERFORMANCE 3.3 VOLT 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH
35
35 ns 18 ns 14 ns 70 ns
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
40
40 ns 20 ns 15 ns 75 ns
45
45 ns 22 ns 17 ns 80 ns
50
50 ns 24 ns 19 ns 90 ns
Features
s 256K x 16-bit organization s EDO Page Mode for a sustained data rate of 71 MHz s RAS access time: 35, 40, 45, 50 ns s Dual CAS Inputs s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, and Self Refresh s Optional Self Refresh (V53C16258SL) s Refresh Interval: Standard: 512 cycles/8ms s Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages s Single +3.3V 0.3V Power Supply s TTL Interface
Description
The V53C16258L is a 262,144 x 16 bit highperformance CMOS dynamic random access memory. The V53C16258L offers Page mode with Extended Data Output. An address, CAS and RAS input capacitances are reduced to one quarter when the x4 DRAM is used to construct the same memory density. The V53C16258L has symmetric address and accepts 512 cycle 8ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits, within a page, with cycle times as short as 15ns. The V53C16258L is ideally suited for a wide variety of high performance portable computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range 0C to 70C Package Outline K * T * 35 * Access Time (ns) 40 * 45 * 50 * Power Std. * Temperature Mark Blank
V53C16258L Rev. 1.1 June 1999
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MOSEL VITELIC
Part Name
V53C16258SLKxx V53C16258SLTxx V53C16258LKxx V53C16258LTxx
V53C16258L
Supply Voltage
3.3V 3.3V 3.3V 3.3V
Self Refresh
Standard Self Refresh (8ms) Standard Self Refresh (8ms) No Self Refresh No Self Refresh
Package
SOJ TSOP SOJ TSOP
Speed
35/40/45/50 35/40/45/50 35/40/45/50 35/40/45/50
40-Pin Plastic SOJ PIN CONFIGURATION Top View
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
16258L-02
V
5
3
C
16
2
5
8
S
L
FAMILY
DEVICE S (Standard Self Refresh) L (3.3V) K (SOJ) T (TSOP-II)
PKG
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL)
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
35 40 45 50
(35 ns) (40 ns) (45 ns) (50 ns)
16258L-01
40/44 Pin Plastic TSOP-II PIN CONFIGURATION Top View
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8
1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35
Pin Names
A0-A8 RAS UCAS LCAS WE OE I/O1-I/O16 VCC VSS NC Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9
NC NC WE RAS NC A0 A1 A2 A3 Vcc
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
16258L-03
NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
V53C16258L Rev. 1.1 June 1999
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Absolute Maximum Ratings*
Ambient Temperature Under Bias ..................................... -10C to +80C Storage Temperature (plastic) ..... -55C to +125C Voltage Relative to VSS .................-1.0 V to +4.6 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C16258L
TA = 25C, VCC = 3.3 V 0.3V, VSS = 0 V
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
Capacitance*
* Note: Capacitance is sampled and not 100% tested
Block Diagram
256K x 16
OE WE UCAS LCAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y -Y8 0
I/O 1 I/O 2 I/O 3
SENSE AMPLIFIERS
512 x 16
I/O BUFFER
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11
REFRESH COUNTER
9 A0 A1
ADDRESS BUFFERS AND PREDECODERS
X0 -X8
ROW DECODERS
512
* * *
A7 A8
MEMORY ARRAY 512 x 512 x 16
I/O 12 I/O 13 I/O 14 I/O 15 I/O 16
16258L-04
V53C16258L Rev. 1.1 June 1999
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DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC = +3.3 V 0.3V, VSS = 0 V, unless otherwise specified.
Access Time V53C16258L Min.
-10
V53C16258L
Symbol
ILI ILO ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Typ.
Max.
10
Unit
A A mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
35 40 45 50
120 110 100 90 1
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 35 40 45 50
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2
120 110 100 90 120 100 90 80 1
mA
ICC4
VCC Supply Current, EDO Page Mode Operation
35 40 45 50
mA
Minimum Cycle
1, 2
ICC5
VCC Supply Current, Standby, Output Enabled other inputs VSS VCC Supply Current, CMOS Standby
mA
RAS=VIH, CAS=VIL
1
ICC6
500
A
RAS VCC - 0.2 V, CAS VCC- 0.2 V, All other inputs VSS RAS = CAS 0.2 V Output Open
ICC7 VCC VIL VIH VOL VOH
VCC Supply Current, Self Refresh Power Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 3.0 -1 2.4 3.3
200
A V V V V V
3.6 0.8 VCC+1 0.4
3 3 IOL = 2 mA IOH = -2 mA
V53C16258L Rev. 1.1 June 1999
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TA = 0C to 70C, VCC = +3.3 V 0.3V, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
35 #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
V53C16258L
AC Characteristics
40
45
50
Symbol
tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH tWP tWCR tRWL tDS
Parameter
RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
35 70 25 35 6 13 0 0 6 0 5 10 5 0 5 10 24 75 40 75 25 40 7 17 0 0 7 0 5 10 5 0 28 75 45 80 25 45 8 18 0 0 8 0 6 10 5 0 32 75K 50 90 30 50 9 19 0 0 9 0 7 10 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4
15
0
0
0
0
ns
5
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7 11 11 35 18 0 0 25 10 10 8 0 5 5 25 10 0 20 6
8 12 12 40 20 0 0 30 12 10 12 0 5 5 30 12 0 20 6
9 13 13 45 22 0 0 35 13 10 13 0 6 6 35 13 0 23 7
10 14 14 50 24 0 0 40 14 10 14 0 7 7 40 14 0 26 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 14 12, 13 11 12 6, 7, 14 6, 8, 9 6, 7, 10 16 16
V53C16258L Rev. 1.1 June 1999
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AC Characteristics (Cont'd)
35 #
33 34 35 36 37
V53C16258L
40
45
50
Symbol
tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tCOH tOES tOEH tOEP tT
Parameter
Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay EDO Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh EDO Page Mode Read-Modify-Write Cycle Time Output Hold After CAS Low OE Low to CAS High Setup Time OE Hold Time from WE during Read-Modify Write Cycle OE High Pulse Width Transition Time (Rise and Fall)
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
5 5 5 90 59 5 6 6 110 75 6 7 7 115 80 7 8 8 130 87 ns ns ns ns ns 14 14 14
38 39
23 46
30 58
32 62
34 68
ns ns
12 12
40 41 42
34 29 14
48 38 15
50 41 17
52 42 19
ns ns ns 12
43 44 45 46 47
4 18 20 25 8
5 20 23 30 10
6 22 25 35 10
7 24 27 40 10
ns ns ns ns ns 7
48 49 50
0 8 43
0 10 60
0 10 65
0 10 70
ns ns ns
51 52 53
3 3 5
5 5 10
5 5 10
5 5 10
ns ns ns
54 55
8 1.5 50
10 1.5 50
10 1.5 50
10 1.5 50
ns ns 15
Optional Self Refresh
56 57 58 59 60 tREF tRASS tRPS tCHS tCHD Refresh Interval (512 Cycles) RAS Pulse Width During Self Refresh RAS Precharge Time During Self Refresh CAS Hold Time Width During Self Refresh CAS Low Time During Self Refresh 100 100 100 100 8 100 100 100 100 8 100 100 100 100 8 100 100 100 100 8 ms s s s s 17 18 18 18 18
V53C16258L Rev. 1.1 June 1999
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Notes:
V53C16258L
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in EDO Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 50 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 500 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval. 18. One CBR refresh or complete set of row refresh cycles must be completed upon exiting Self Refresh mode.
V53C16258L Rev. 1.1 June 1999
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Truth Table
Function
Standy Read: Word Read: Lower Byte
V53C16258L
RAS
H L L
LCAS
H L L
UCAS
H L H
WE
X H H
OE
X L L
ADDRESS
X ROW/COL ROW/COL
I/O
High-Z Data Out Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-In Data-Out, Data-In Data-Out High-Z High-Z High-Z
Notes
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early-Write) Write: Lower Byte (Early)
L L
L L
L H
L L
X X
ROW/COL ROW/COL
Read: Upper Byte (Early)
L
H
L
L
X
ROW/COL
Read-Write EDO Page-Mode Read EDO Page-Mode Write EDO Page-Mode Read-Write Hidden Refresh Read RAS-Only Refresh CBR Refresh Self Refresh
L L L L LHL L HL HL
L HL HL HL L H L L
L HL HL HL L H L L
HL H L HL H X X X
LH L X LH L X X X
ROW/COL COL COL COL ROW/COL ROW X X
1,2 2 2 1,2 2
3
Notes:
1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS).
V53C16258L Rev. 1.1 June 1999
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Waveforms of Read Cycle
t RAS (1) t RC (2) t RP (3)
V53C16258L
RAS
VIH VIL t CRP (13)
t AR (23)
t RCD (6) t RAD (24)
t CSH (4)
CAS UCAS, LCAS
VIH VIL t ASR (8) t RAH (9)
t RSH (R)(12) t CAS (5)
t CRP (13)
t ASC (10)
t CAH (11)
ADDRESS
VIH VIL
ROW ADDRESS
COLUMN ADDRESS t CAR (44) t RCH (14) t RRH (15)
t RCS (7) WE VIH VIL
t ROH (16) t CAA (20) t OAC (17) t OES (52)
OE
VIH VIL
I/O
VOH VOL
t RAC (19)
t CAC (18)
t HZ (22) VALID DATA-OUT
t HZ (22)
t LZ (21)
676 01
Waveforms of Early Write Cycle
t RC (2) t RAS (1) RAS VIH V IL t CSH (4) tCRP (13) VIH t RCD (6) t RSH (W)(25) t CAS (5) t CRP (13) tAR (23) t RP (3)
UCAS, LCAS
V IL t RAH (9) tASR (8) tASC (10) ROW ADDRESS t RAD (24) t CWL (26) VIH V IL t WCR (30) t RWL (31) VIH V IL t DHR (46) tDS (32) tDH (33) VALID DATA-IN HIGH-Z
676 02
t CAR (44) t CAH (11)
ADDRESS
VIH V IL
COLUMN ADDRESS t WCH (28) t WP(29) tWCS (27)
WE
OE
I/O
VIH V IL
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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Waveforms of OE-Controlled Write Cycle
t AR (23) t RAS (1) t RC (2) t RP (3)
V53C16258L
RAS
V IH V IL t CRP (13)
t RCD (6)
t CSH (4)
UCAS, LCAS CAS
V IH V IL t RAD (24) t RAH (9)
t RSH (W)(12) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
t ASR (8) ADDRESS V IH V IL
ROW ADDRESS
COLUMN ADDRESS t CWL (26) t RWL (31)
t WP (29) WE V IH V IL
t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN
676 03
I/O
Waveforms of Read-Modify-Write Cycle
t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) CAS UCAS, LCAS VIH VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t ACS VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O VIH VIL VOH VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN
675 04
t RP (3)
t AR (23)
t RCD (6)
t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26)
t CRP (13)
CAH (11)
t RWD (39)
t WP (29)
WE
t CAA (20) t OAC (17) t OEH (53) t DH (33)
OE
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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Waveforms of EDO Page Mode Read Cycle
RAS V IH V IL t AR (23) t RCD (6) t CRP (13) UCAS, LCAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) t RCS (7) t CAR (44) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t CRP (13) t CAS (5) t RAS (1)
V53C16258L
t
RP (3)
t CAS (5)
t ASR (8) ADDRESS V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
t CAH (11) COLUMN ADDRESS t RCS (7) t RCH (14)
COLUMN ADDRESS
WE
V IH V IL t CAP (45) t OES (52) t OEP (54) t CAC (18) t CAA (20) t OAC (17) t RRH (15)
t CAC (18) t COH (5)
t HZ (22) t HZ (22) t HZ (22) VALID DATA OUT
t HZ (22) VALID DATA OUT t LZ
I/O
V OH V OL
VALID DATA OUT
2736 09
Waveforms of EDO Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) UCAS, LCAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL
ROW ADD COLUMN ADDRESS
t RP (3) t RAS (1)
t PC (42) t CP (43) t CAS (5)
t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
OE
VIH V IL t DS (32) t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
t DS (32)
t DH (33)
VALID DATA IN
I/O
V IH V IL
OPEN
OPEN 2736 10
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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Waveforms of EDO Page Mode Read-Write Cycle
RAS VIH V
IL
V53C16258L
t RAS (1)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V UCAS, LCAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RWD (39) t CWD (38) V WE V
IH IL
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17) t OEH (53) t CAA (20) t CAP (43)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN 2736 11
IN
t LZ
t LZ
Waveforms of RAS-Only Refresh Cycle
t RC (2) t RP (3)
RAS VIH V IL t CRP (13) VIH V IL tASR (8) t RAH (9) VIH V IL t RAS (1)
UCAS, LCAS
ADDRESS
ROW ADD
2736 12
NOTE: WE, OE = Don't care
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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Waveforms of CAS-before-RAS Refresh Counter Test Cycle
V53C16258L
t RAS (1)
RAS
t RP (3)
VIH V IL t CSR (47) t CHR (49) t CP(43) t RSH (W)(25) tCAS (5)
UCAS, LCAS
VIH V IL VIH V IL READ CYCLE t RRH (15) t RCH (14)
ADDRESS
t RCS (7)
WE
VIH V IL t ROH (16) t OAC (17)
OE
VIH V IL t LZ (21) t HZ (22) t HZ (22) DOUT t RWL (31) t CWL (26) t WCS (27) t WCH (28)
I/O
VOH VOL WRITE CYCLE
WE
VIH V IL VIH V IL tDS (32) t DH (33) D IN
676 12
OE
I/O
VIH V IL
Waveforms of CAS-before-RAS Refresh Cycle
t RP (3) RAS V IH V IL t CP (43) V IH V IL t HZ (22) I/O V OH V OL NOTE: WE, OE, A0-A8 = Don't care
Don't Care Undefined
675 07
t RC (2) t RAS (1) t RP (3)
t RPC (48) t CSR (47)
t CHR (49)
CAS
V53C16258L Rev. 1.1 June 1999
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Waveforms of Hidden Refresh Cycle (Read)
tRC (2) VIH V IL tRCD (6) t CRP (13) UCAS, LCAS VIH V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL t CAA (20) VIH V IL t CAC (18) t LZ (21) t RAC (19) VOH I/O VOL VALID DATA t HZ (22) t OAC (17)
ROW ADD
V53C16258L
t RAS (1) tAR (23)
t RP (3)
tRC (2) t RAS (1)
t RP (3)
RAS
tRSH (R)(12)
t CHR (49)
tCRP (13)
tRAD (24) tASC (10) t CAH (11)
COLUMN ADDRESS
tRCS (7) WE
t RRH (15)
OE
t HZ (22)
676 10
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) VIH V IL t RCD (6) t CRP (13) UCAS, LCAS VIH V IL tASR (8) t RAH (9) ADDRESS VIH V IL VIH V IL VIH V IL t DS (32) VIH I/O V IL tDH (33)
VALID DATA-IN ROW ADD
t RC (2) tRP (3) t RAS (1) tRP (3)
t RAS (1) tAR (23)
RAS
t RSH (12)
t CHR (49)
t CRP (13)
tRAD (24) tASC (10) t CAH (11)
COLUMN ADDRESS
t WCS (27) WE
t WCH (28)
OE
t DHR (46)
676 11
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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MOSEL VITELIC
V53C16258L
Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRAS RAS V IH V IL tCSH tPC tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tCAR tRCD tCAS(5) tCP tCAS tPC tCP tRSH tCAS tCP tRP(3)
UCAS, LCAS
ADDRESS
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
tRCS V IH V IL tRAC tCAC tOE V IH OE V IL
tRCH tWCS tWCH
WE
tCAA tCAP
tCAA
tCAC(18)
tDS
tDH
tCOH VOH I/O VOL
VALID DATA OUT VALID DATA OUT VALID DATA IN
Waveforms of Self Refresh Cycle (Optional)
t RP (3)
RAS
t RASS (57)
t RPS (58)
VIH V IL
tRPC (48) tCP (43) tCSR (47) tCHD (60) tCHS (59) tRPC (48)
UCAS, LCAS
VIH V IL
ADDRESS
VIH V IL
I/O
VOH VOL
OPEN
WE
VIH V IL
OE
VIH V IL
16258L 05
Don't Care
Undefined
V53C16258L Rev. 1.1 June 1999
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MOSEL VITELIC
Functional Description
The V53C16258L is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C16258L reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C16258L
Extended Data Output Page Mode
EDO Page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Hyper Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 71 MHz for applications that require high bandwidth such as bitmapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 512 Data Rate = ---------------------------------------t RC + 511 x t PC
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Self Refresh
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of inactivity. Device operation in this mode provides additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initiated with a CAS before RAS (CBR) Refresh cycle, holding both RAS low (tRASS) and CAS low (tCHD) for a specified period. Both of these parameters are specified with minimum values to guarantee entry into Self Refresh operation. Once the device has been placed in to Self Refresh mode the CAS clock is no longer required to maintain Self Refresh operation. The Self Refresh mode is terminated by returning the RAS clock to a high level for a specified (tRPS)
V53C16258L Rev. 1.1 June 1999
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MOSEL VITELIC
minimum time. After termination of the Self Refresh cycle normal accesses to the device may be initiated immediately, providing that subsequent refresh cycles utilize the CAS before RAS (CBR) mode of operation.
V53C16258L
Table 1. V53C16258L Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
Data Output Operation
The V53C16258L Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C16258L is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
V53C16258L Rev. 1.1 June 1999
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MOSEL VITELIC
Package Diagram
40-Pin Plastic SOJ
1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 21
V53C16258L
Unit in inches [mm]
0.400 0.005 [10.16 0.127]
0.440 0.005 [11.18 0.127]
1
20 0.026 MIN [0.660 MIN] 0.144 MAX [3.66 MAX]
0.010
+ 0.004 - 0.002
+0.004 0.025 -0.002
+0.102 0.635 -0.051
+0.102 0.254 -0.051
0.050 0.006 [1.27 0.152]
0.04 [0.1]
0.018
+0.004 -0.002
+0.102 0.457 -0.051
40/44L-Pin TSOP-II
0.0047 - 0.0083 [0.119 - .211] 40 21 Unit in inches [mm]
0.017 - 0.023 [0.432 - 0.584]
0.462 - 0.470 [11.73 - 11.94]
0.396 - 0.404 [10.06 - 10.26]
1 0.0315 BSC [.8001 BSC] 0.039 - 0.047 [0.991 - 1.193] 0.721 - 0.729 [18.31 - 18.52] 0.012 - 0.016 [0.305 - 0.406]
20 0-5 0.002 - 0.008 [0.051 - 0.203] BASE PLANE SEATING PLANE
V53C16258L Rev. 1.1 June 1999
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0.368 0.010 [9.35 0.254]
MOSEL VITELIC
Notes:
V53C16258L
V53C16258L Rev. 1.1 June 1999
19
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-578-3344 FAX: 886-3-579-2838
V53C16258L
GERMANY (CONTINENTAL EUROPE & ISRAEL )
71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
JAPAN
WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 81-43-299-6000 FAX: 81-43-299-6555
HONG KONG
19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 852-2665-4883 FAX: 852-2664-7535
IRELAND & UK
BLOCK A UNIT 2 BROOMFIELD BUSINESS PARK MALAHIDE CO. DUBLIN, IRELAND PHONE: +353 1 8038020 FAX: +353 1 8038049
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
SOUTHWESTERN
SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
(c) Copyright 1998, MOSEL VITELIC Inc.
6/99 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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